The present invention relates to semiconductor devices and more particularly to a semiconductor device having a static random access memory.
In a semiconductor device called SOC (System On Chip), a logic circuit and a memory cell are mounted on a single chip. Given below is an explanation of a semiconductor device of that type which has an SRAM (Static Random Access Memory) memory cell.
The SRAM memory cell includes a flip-flop with two cross-coupled inverters and two access transistors. The flip-flop has two cross-coupled storage nodes. One access transistor is electrically coupled between one storage node and one bit line. The other access transistor is electrically coupled between the other storage node and the other bit line. The gates of the two access transistors are electrically coupled to a word line.
Also in the flip-flop, one driver transistor is electrically coupled between the one storage node and a grounding wiring and the other driver transistor is electrically coupled between the other storage node and the grounding wiring. One load transistor is electrically coupled between the one storage node and a voltage supply wiring and the other load transistor is electrically coupled between the other storage node and the voltage supply wiring.
The gate of the one driver transistor, the gate of the one load transistor, and the other storage node are electrically coupled to each other. Also, the gate of the other driver transistor, the gate of the other load transistor, and the one storage node are electrically coupled to each other.
In a region of a semiconductor substrate in which an SRAM memory cell is formed, two access transistors, two driver transistors and two load transistors are formed in prescribed element formation regions respectively. Above them, a multilayer interconnection structure including first, second and third wirings for coupling the transistors electrically is formed. The second wirings include bit lines and a voltage supply wiring. The third wirings include a word line and grounding wires.
One of the documents which disclose a multilayer interconnection structure is Japanese Unexamined Patent Publication No. 2010-135572. One of the documents which disclose an SRAM is Japanese Unexamined Patent Publication No. 2007-103862.